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| ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY FLASH AND SRAM COMBO MEMORY FEATURES * Flexible dual-bank architecture * Support for true concurrent operations with no latency: Read bank b during program bank a and vice versa Read bank b during erase bank a and vice versa * Organization: 4,096K x 16 (Flash) 512K x 16 (SRAM) * Basic configuration: Flash Bank a (16Mb Flash for data storage) - Eight 4K-word parameter blocks - Thirty-one 32K-word blocks Bank b (48Mb Flash for program storage) - Ninety-six 32K-word main blocks SRAM 8Mb SRAM for data storage - 512K-words * F_VCC, VCCQ, F_VPP, S_VCC voltages MT28C6428P20 1.80V (MIN)/2.20V (MAX) F_VCC read voltage 1.80V (MIN)/2.20V (MAX) S_VCC read voltage 1.80V (MIN)/2.20V (MAX) VCCQ MT28C6428P18 1.70V (MIN)/1.90V (MAX) F_VCC read voltage 1.70V (MIN)/1.90V (MAX) S_VCC read voltage 1.70V (MIN)/1.90V (MAX) VCCQ MT28C6428P20/P18 1.80V (TYP) F_VPP (in-system PROGRAM/ERASE) 1.0V (MIN) S_VCC (SRAM data retention) 12V 5% (HV) F_VPP (in-house programming and accelerated programming algorithm [APA] activation) * Asynchronous access time Flash access time: 80ns @ 1.80V F_VCC SRAM access time: 80ns @ 1.80V S_VCC * Page Mode read access Interpage read access: 80ns @ 1.80V F_VCC Intrapage read access: 30ns @ 1.80V F_VCC * Low power consumption * Enhanced suspend options ERASE-SUSPEND-to-READ within same bank PROGRAM-SUSPEND-to-READ within same bank ERASE-SUSPEND-to-PROGRAM within same bank * Read/Write SRAM during program/erase of Flash MT28C6428P20 MT28C6428P18 Low Voltage, Extended Temperature 0.18m Process Technology BALL ASSIGNMENT 67-Ball FBGA (Top View) 1 A B C D E F G H NC NC NC 2 NC 3 A20 4 A11 5 A15 6 A14 7 A13 8 A12 9 F_VSS 10 VccQ 11 NC 12 NC A16 A8 A10 A9 DQ15 S_WE# DQ14 DQ7 F_WE# NC A21 DQ13 DQ6 DQ4 DQ5 VSS F_RP# DQ12 S_CE2 S_VCC F_VCC F_WP# F_VPP A19 DQ11 DQ10 DQ2 DQ3 S_LB# S_UB# S_OE# DQ9 DQ8 DQ0 DQ1 A18 A17 A7 A6 A3 A2 A1 S_CE1# F_VCC A5 A4 A0 F_CE# F_VSS F_OE# NC NC NC Top View (Ball Down) * Dual 64-bit chip protection registers for security purposes * PROGRAM/ERASE cycles 100,000 WRITE/ERASE cycles per block * Cross-compatible command set support Extended command set Common flash interface (CFI) compliant OPTIONS * Timing 80ns 85ns * Boot Block Configuration Top Bottom * Operating Voltage Range F_VCC = 1.70V-1.90V F_VCC = 1.80V-2.20V * Operating Temperature Range Commercial (0oC to +70oC) Extended (-40oC to +85oC) * Package 67-ball FBGA (8 x 8 grid) Part Number Example: MARKING -80 -85 T B 18 20 None ET FM MT28C6428P20FM-80 BET 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 1 (c)2002, Micron Technology, Inc. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY GENERAL DESCRIPTION The MT28C6428P20 and MT28C6428P18 combination Flash and SRAM memory devices provide a compact, low-power solution for systems where PCB real estate is at a premium. The dual-bank Flash devices are high-performance, high-density, nonvolatile memory with a revolutionary architecture that can significantly improve system performance. This new architecture features: * A two-memory-bank configuration supporting dual-bank operation; * A high-performance bus interface providing a fast page data transfer; and * A conventional asynchronous bus interface. The devices also provide soft protection for blocks by configuring soft protection registers with dedicated command sequences. For security purposes, dual 64bit chip protection registers are provided. The embedded WORD WRITE and BLOCK ERASE functions are fully automated by an on-chip write state machine (WSM). The WSM simplifies these operations and relieves the system processor of secondary tasks. An on-chip status register, one for each bank, can be used to monitor the WSM status to determine the progress of a PROGRAM/ERASE command. The erase/program suspend functionality allows compatibility with existing EEPROM emulation software packages. The devices take advantage of a dedicated power source for the Flash memory (F_VCC) and a dedicated power source for the SRAM (S_VCC), both at 1.70V-2.20V for optimized power consumption and improved noise immunity. A dedicated I/O power supply (VCCQ) is provided with an extended range (1.70V-2.20V), to allow a direct interface to most common logic controllers and to ensure improved noise immunity. The separate S_VCC pin for the SRAM provides data retention capability when required. The data retention S_VCC is specified as low as 1.0V. The MT28C6428P20 and MT28C6428P18 devices support two F_VPP voltage ranges, an in-circuit voltage of 0.9V-2.2V and a production compatibility voltage of 12V 5%. The 12V 5% F_VPP2 is supported for a maximum of 100 cycles and 10 cumulative hours. The MT28C6428P20 and MT28C6428P18 contain an asynchronous 8Mb SRAM organized as 512K-words by 16 bits. The devices are fabricated using an advanced CMOS process and high-speed/ultra-lowpower circuit technology, and then are packaged in a 67-ball FBGA package with 0.80mm pitch. ARCHITECTURE AND MEMORY ORGANIZATION The Flash devices contain two separate banks of memory (bank a and bank b) for simultaneous READ and WRITE operations, which are available in the following bank segmentation configuration: * Bank a comprises one-fourth of the memory and contains 8 x 4K-word parameter blocks, while the remainder of bank a is split into 31 x 32K-word blocks. * Bank b represents three-fourths of the memory, is equally sectored, and contains 96 x 32K-word blocks. Figures 2 and 3 show the bottom and top memory organizations. DEVICE MARKING Due to the size of the package, Micron's standard part number is not printed on the top of each device. Instead, an abbreviated device mark comprised of a five-digit alphanumeric code is used. The abbreviated device marks are cross referenced to Micron part numbers in Table 1. Table 1 Cross Reference for Abbreviated Device Marks PART NUMBER MT28C6428P20FM-80 BET MT28C6428P20FM-80 TET MT28C6428P18FM-85 BET MT28C6428P18FM-85 TET PRODUCT MARKING FW454 FW453 FW455 FW452 SAMPLE MARKING FX454 FX453 FX455 FX452 MECHANICAL SAMPLE MARKING FY454 FY453 FY455 FY452 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY PART NUMBERING INFORMATION Micron's low-power devices are available with several different combinations of features (see Figure 1). Valid combinations of features and their corresponding part numbers are listed in Table 2. Figure 1 Part Number Chart MT 28C 642 8 P 20 FM-80 T ET Micron Technology Flash Family 28C = Dual-Supply Flash/SRAM Combo Operating Temperature Range None = Commercial (0C to +70C) ET = Extended (-40C to +85C) Boot Block Starting Address B = Bottom boot T = Top boot Density/Organization/Banks 642 = 64Mb (4,096K x 16) bank a = 1/4; bank b = 3/4 Access Time -80 = 80ns -85 = 85ns SRAM Density 8 = 8Mb SRAM (512K x 16) Read Mode Operation P = Asynchronous/Page Read Package Code FM = 67-ball FBGA (8 x 8 grid) Operating Voltage Range 20 = 1.80V-2.20V VCC 18 = 1.70V-1.90V Table 2 Valid Part Number Combinations1 ACCESS TIME (ns) 80 80 85 85 BOOT BLOCK STARTING ADDRESS Bottom Top Bottom Top OPERATING TEMPERATURE RANGE -40oC to +85oC -40oC to +85oC -40oC to +85oC -40oC to +85oC PART NUMBER MT28C6428P20FM-80 BET MT28C6428P20FM-80 TET MT28C6428P18FM-85 BET MT28C6428P18FM-85 TET NOTE: 1. For part number combinations not listed in this table, please contact your Micron representative. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY BLOCK DIAGRAM F_WE# F_OE# F_CE# F_RP# A19-A20 F_VCC FLASH F_VPP Bank a F_WP# F_VSS 4,096K x 16 Bank b VCCQ DQ0-DQ15 SRAM 512K x 16 S_VCC A0-A18 S_CE1# S_CE2 S_OE# S_WE# S_VSS S_UB# S_LB# FLASH FUNCTIONAL BLOCK DIAGRAM PR Lock PR Lock Query Query/OTP OTP DQ0-DQ15 X DEC Data Input Buffer Data Register F_RST# F_CE# F_WE# F_OE# Y/Z DEC Bank 1 Blocks Y/Z Gating/Sensing Manufacturer's ID Device ID Block Lock RCR ID Reg. CSM Status Reg. WSM Program/ Erase Pump Voltage Generators Output Multiplexer DQ0-DQ15 I/O Logic Output Buffer A0-A21 Address Input Buffer Address CNT/WSM Address Multiplexer Y/Z DEC X DEC Y/Z Gating/Sensing Bank 2 Blocks Address Latch 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY BALL DESCRIPTIONS 67-BALL FBGA NUMBERS H6, H5, B4, A8, B3, G9, G8, G7, H4, G6, G5, B6, B5, A4, A7, A6, A5, G4, G3, E5, A3, C5 H7 H9 C3 D4 SYMBOL A0-A21 TYPE Input DESCRIPTION Address Inputs: Inputs for the addresses during READ and WRITE operations. Addresses are internally latched during READ and WRITE cycles. Flash: A0-A21; SRAM: A0-A18. F_CE# F_OE# F_WE# F_RP# Input Input Input Input Flash Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby power mode. Flash Output Enable: Enables Flash output buffers when LOW. When F_OE# is HIGH, the output buffers are disabled. Flash Write Enable: Determines if a given cycle is a Flash WRITE cycle. F_WE# is active LOW. Reset. When F_RP# is a logic LOW, the device is in reset, which drives the outputs to High-Z and resets the WSM. When F_RP# is a logic HIGH, the device is in standard operation. When F_RP# transitions from logic LOW to logic HIGH, the device resets all blocks to locked and defaults to the read array mode. Flash Write Protect. Controls the lock down function of the flexible locking feature. SRAM Chip Enable1: Activates the SRAM when it is LOW. HIGH level deselects the SRAM and reduces the power consumption to standby levels. SRAM Chip Enable2: Activates the SRAM when it is HIGH. LOW level deselects the SRAM and reduces the power consumption to standby levels. SRAM Output Enable: Enables SRAM output buffers when LOW. When S_OE# is HIGH, the output buffers are disabled. SRAM Write Enable: Determines if a given cycle is an SRAM WRITE cycle. S_WE# is active LOW. SRAM Lower Byte: When LOW, it selects the SRAM address lower byte (DQ0-DQ7). SRAM Upper Byte: When LOW, it selects the SRAM address upper byte (DQ8-DQ15). Data Inputs/Outputs: Input array data on the second CE# and WE# cycle during PROGRAM command. Input commands to the command user interface when CE# and WE# are active. Output data when CE# and OE# are active. E3 G10 F_WP# S_CE1# Input Input D8 S_CE2 Input F5 B8 F3 F4 S_OE# S_WE# S_LB# S_UB# Input Input Input Input F9, F10, E9, DQ0-DQ15 Input/ E10, C9, C10, Output C8, B10, F8, F7, E8, E6, D7, C7, B9, B7 (continued on next page) 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY BALL DESCRIPTIONS (continued) 67-BALL FBGA NUMBERS E4 SYMBOL F_VPP TYPE Input/ Supply DESCRIPTION Flash Program/Erase Power Supply: [0.9V-2.2V or 11.4V-12.6V]. Operates as input at logic levels to control complete device protection. Provides backward compatibility for factory programming when driven to 11.4V-12.6V. A lower F_VPP voltage range (0.0V-2.2V) is available. Contact factory for more information. Flash Power Supply: [1.70V-1.90V or 1.80V-2.20V]. Supplies power for device operation. Flash Specific Ground: Do not float any ground ball. SRAM Power Supply: [1.70V-1.90V or 1.80V-2.20V]. Supplies power for device operation. SRAM Specific Ground: Do not float any ground ball. I/O Power Supply: [1.70-1.90V or 1.80V-2.20V]. No Connect: Lead is not internally connected; it may be driven or floated. D10, H3 A9, H8 D9 D3 A10 A1, A2, A11, A12, C4, H1, H2, H10, H11, H12 C6, D5, D6, E7, F6 F_VCC F_VSS S_VCC S_VSS VCCQ NC Supply Supply Supply Supply Supply - - - Contact balls not mounted; corresponding position on PCB can be used to reduce routing complexity. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY TRUTH TABLE - FLASH MODES Read Write Standby Output Disable Reset FLASH SIGNALS SRAM SIGNALS F_RP# F_CE# F_OE# F_WE# S_CE1# S_CE2 S_OE# S_WE# S_UB# S_LB# H H H H L L L H L X L H X H X H L X H X SRAM must be High-Z MEMORY OUPUT MEMORY DQ0-DQ15 BUS CONTROL Flash Flash Other Other Other DOUT DIN High-Z High-Z High-Z NOTES 1, 2, 3 1 4 4, 5 4, 6 SRAM any mode allowable TRUTH TABLE - SRAM MODES Read DQ0-DQ15 DQ0-DQ7 DQ8-DQ15 Write DQ0-DQ15 DQ0-DQ7 DQ8-DQ15 Standby Output Disable NOTE: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. FLASH SIGNALS SRAM SIGNALS F_RP# F_CE# F_OE# F_WE# S_CE1# S_CE2 S_OE# S_WE# S_UB# S_LB# MEMORY OUPUT MEMORY DQ0-DQ15 BUS CONTROL SRAM SRAM SRAM SRAM SRAM SRAM Other Other Other DOUT DOUT LB DOUT UB DIN DIN LB DIN UB High-Z High-Z High-Z NOTES Flash must be High-Z L L L L L L H X L H H H H H H X L H L L L H H H X X X H H H L L L X X X L H L L H L X X X L L H L L H X X X 1, 3 7 8 1, 3 9 10 4 4 4 Flash any mode allowable Two devices may not drive the memory bus at the same time. Allowable Flash read modes include read array, read query, read configuration, and read status. Outputs are dependent on a separate device controlling bus outputs. Modes of the Flash and SRAM can be interleaved so that while one is disabled, the other controls outputs. SRAM is enabled and/or disabled with the logical function: S_CE1# or S_CE2. Simultaneous operations can exist, as long as the operations are interleaved such that only one device attempts to control the bus outputs at a time. Data output on lower byte only; upper byte High-Z. Data output on upper byte only; lower byte High-Z. Data input on lower byte only. Data input on upper byte only. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY FLASH Figure 2 Bottom Boot Block Device Block 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 Bank b = 48Mb Block Size Address Range (K-bytes/ (x16) K-words) 64/32 3F8000h-3FFFFFh 64/32 3F0000h-3F7FFFh 64/32 3E8000h-3EFFFFh 64/32 3E0000h-3E7FFFh 64/32 3D8000h-3DFFFFh 64/32 3D0000h-3D7FFFh 64/32 3C8000h-3CFFFFh 64/32 3C0000h-3C7FFFh 64/32 3B8000h-3BFFFFh 64/32 3B0000h-3B7FFFh 64/32 3A8000h-3AFFFFh 64/32 3A0000h-3A7FFFh 64/32 398000h-39FFFFh 64/32 390000h-397FFFh 64/32 388000h-38FFFFh 64/32 380000h-387FFFh 64/32 378000h-37FFFFh 64/32 370000h-377FFFh 64/32 368000h-36FFFFh 64/32 360000h-367FFFh 64/32 358000h-35FFFFh 64/32 350000h-357FFFh 64/32 348000h-34FFFFh 64/32 340000h-347FFFh 64/32 338000h-33FFFFh 64/32 330000h-337FFFh 64/32 328000h-32FFFFh 64/32 320000h-327FFFh 64/32 318000h-31FFFFh 64/32 310000h-317FFFh 64/32 308000h-30FFFFh 64/32 300000h-307FFFh 64/32 2F8000h-2FFFFFh 64/32 2F0000h-2F7FFFh 64/32 2E8000h-2EFFFFh 64/32 2E0000h-2E7FFFh 64/32 2D8000h-2DFFFFh 64/32 2D0000h-2D7FFFh 64/32 2C8000h-2CFFFFh 64/32 2C0000h-2C7FFFh 64/32 2B8000h-2BFFFFh 64/32 2B0000h-2B7FFFh 64/32 2A8000h-2AFFFFh 64/32 2A0000h-2A7FFFh 64/32 298000h-29FFFFh 64/32 290000h-297FFFh 64/32 288000h-28FFFFh 64/32 280000h-287FFFh Block 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 Bank b = 48Mb Block Size Address Range (K-bytes/ (x16) K-words) 64/32 278000H-27FFFFh 64/32 270000h-277FFFh 64/32 268000h-26FFFFh 64/32 260000h-267FFFh 64/32 258000h-25FFFFh 64/32 250000h-257FFFh 64/32 248000h-24FFFFh 64/32 240000h-247FFFh 64/32 238000h-23FFFFh 64/32 230000h-237FFFh 64/32 228000h-22FFFFh 64/32 220000h-227FFFh 64/32 218000h-21FFFFh 64/32 210000h-217FFFh 64/32 208000h-20FFFFh 64/32 200000h-207FFFh 64/32 1F8000h-1FFFFFh 64/32 1F0000h-1F7FFFh 64/32 1E8000h-1EFFFFh 64/32 1E0000h-1E7FFFh 64/32 1D8000h-1DFFFFh 64/32 1D0000h-1D7FFFh 64/32 1C8000h-1CFFFFh 64/32 1C0000h-1C7FFFh 64/32 1B8000h-1BFFFFh 64/32 1B0000h-1B7FFFh 64/32 1A8000h-1AFFFFh 64/32 1A0000h-1A7FFFh 64/32 198000h-19FFFFh 64/32 190000h-197FFFh 64/32 188000h-18FFFFh 64/32 180000h-187FFFh 64/32 178000h-17FFFFh 64/32 170000h-177FFFh 64/32 168000h-16FFFFh 64/32 160000h-167FFFh 64/32 158000h-15FFFFh 64/32 150000h-157FFFh 64/32 148000h-14FFFFh 64/32 140000h-147FFFh 64/32 138000h-13FFFFh 64/32 130000h-137FFFh 64/32 128000h-12FFFFh 64/32 120000h-127FFFh 64/32 118000h-11FFFFh 64/32 110000h-117FFFh 64/32 108000h-10FFFFh 64/32 100000h-107FFFh Block 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bank a = 16Mb Block Size Address Range (K-bytes/ (x16) K-words) 64/32 0F8000h-0FFFFFh 64/32 0F0000h-0F7FFFh 64/32 0E8000h-0EFFFFh 64/32 0E0000h-0E7FFFh 64/32 0D8000h-0DFFFFh 64/32 0D0000h-0D7FFFh 64/32 0C8000h-0CFFFFh 64/32 0C0000h-0C7FFFh 64/32 0B8000h-0BFFFFh 64/32 0B0000h-0B7FFFh 64/32 0A8000h-0AFFFFh 64/32 0A0000h-0A7FFFh 64/32 098000h-097FFFh 64/32 090000h-097FFFh 64/32 088000h-087FFFh 64/32 080000h-087FFFh 64/32 078000h-07FFFFh 64/32 070000h-077FFFh 64/32 068000h-067FFFh 64/32 060000h-067FFFh 64/32 058000h-05FFFFh 64/32 050000h-057FFFh 64/32 048000h-04FFFFh 64/32 040000h-047FFFh 64/32 038000h-03FFFFh 64/32 030000h-037FFFh 64/32 028000h-02FFFFh 64/32 020000h-027FFFh 64/32 018000h-01FFFFh 64/32 010000h-017FFFh 64/32 008000h-00FFFFh 8/4 007000h-007FFFh 8/4 006000h-006FFFh 8/4 005000h-005FFFh 8/4 004000h-004FFFh 8/4 003000h-003FFFh 8/4 002000h-002FFFh 8/4 001000h-001FFFh 8/4 000000h-000FFFh 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY FLASH Figure 3 Top Boot Block Device Block 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 Bank a = 16Mb Block Size Address Range (K-bytes/ (x16) K-words) 8/4 3FF000h-3FFFFFh 8/4 3FE000h-3FEFFFh 8/4 3FD000h-3FDFFFh 8/4 3FC000h-3FCFFFh 8/4 3FB000h-3FBFFFh 8/4 3FA000h-3FAFFFh 8/4 3F9000h-3F9FFFh 8/4 3F8000h-3F8FFFh 64/32 3F0000h-3F7FFFh 64/32 3E8000h-3EFFFFh 64/32 3E0000h-3E7FFFh 64/32 3D8000h-3DFFFFh 64/32 3D0000h-3D7FFFh 64/32 3C8000h-3CFFFFh 64/32 3C0000h-3C7FFFh 64/32 3B8000h-3BFFFFh 64/32 3B0000h-3B7FFFh 64/32 3A8000h-3AFFFFh 64/32 3A0000h-3A7FFFh 64/32 398000h-39FFFFh 64/32 390000h-397FFFh 64/32 388000h-38FFFFh 64/32 380000h-387FFFh 64/32 378000h-37FFFFh 64/32 370000h-377FFFh 64/32 368000h-36FFFFh 64/32 360000h-367FFFh 64/32 358000h-35FFFFh 64/32 350000h-357FFFh 64/32 348000h-34FFFFh 64/32 340000h-347FFFh 64/32 338000h-33FFFFh 64/32 330000h-337FFFh 64/32 328000h-32FFFFh 64/32 320000h-327FFFh 64/32 318000h-31FFFFh 64/32 310000h-317FFFh 64/32 308000h-30FFFFh 64/32 300000h-307FFFh Block 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Bank b = 48Mb Block Size Address Range (K-bytes/ (x16) K-words) 64/32 2F8000h-2FFFFFh 64/32 2F0000h-2F7FFFh 64/32 2E8000h-2EFFFFh 64/32 2E0000h-2E7FFFh 64/32 2D8000h-2DFFFFh 64/32 2D0000h-2D7FFFh 64/32 2C8000h-2CFFFFh 64/32 2C0000h-2C7FFFh 64/32 2B8000h-2BFFFFh 64/32 2B0000h-2B7FFFh 64/32 2A8000h-2AFFFFh 64/32 2A0000h-2A7FFFh 64/32 298000h-29FFFFh 64/32 290000h-297FFFh 64/32 288000h-28FFFFh 64/32 280000h-287FFFh 64/32 278000h-27FFFFh 64/32 270000h-277FFFh 64/32 268000h-26FFFFh 64/32 260000h-267FFFh 64/32 258000h-25FFFFh 64/32 250000h-257FFFh 64/32 248000h-24FFFFh 64/32 240000h-247FFFh 64/32 238000h-23FFFFh 64/32 230000h-237FFFh 64/32 228000h-22FFFFh 64/32 220000h-227FFFh 64/32 218000h-21FFFFh 64/32 210000h-217FFFh 64/32 208000h-20FFFFh 64/32 200000h-207FFFh 64/32 1F8000h-1FFFFFh 64/32 1F0000h-1F7FFFh 64/32 1E8000h-1EFFFFh 64/32 1E0000h-1E7FFFh 64/32 1D8000h-1DFFFFh 64/32 1D0000h-1D7FFFh 64/32 1C8000h-1CFFFFh 64/32 1C0000h-1C7FFFh 64/32 1B8000h-1BFFFFh 64/32 1B0000h-1B7FFFh 64/32 1A8000h-1AFFFFh 64/32 1A0000h-1A7FFFh 64/32 198000h-19FFFFh 64/32 190000h-197FFFh 64/32 188000h-18FFFFh 64/32 180000h-187FFFh Block 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bank b = 48Mb Block Size Address Range (K-bytes/ (x16) K-words) 64/32 178000h-17FFFFh 64/32 170000h-177FFFh 64/32 168000h-16FFFFh 64/32 160000h-167FFFh 64/32 158000h-15FFFFh 64/32 150000h-157FFFh 64/32 148000h-14FFFFh 64/32 140000h-147FFFh 64/32 138000h-13FFFFh 64/32 130000h-137FFFh 64/32 128000h-12FFFFh 64/32 120000h-127FFFh 64/32 118000h-11FFFFh 64/32 110000h-117FFFh 64/32 108000h-10FFFFh 64/32 100000h-107FFFh 64/32 0F8000h-0FFFFFh 64/32 0F0000h-0F7FFFh 64/32 0E8000h-0EFFFFh 64/32 0E0000h-0E7FFFh 64/32 0D8000h-0DFFFFh 64/32 0D0000h-0D7FFFh 64/32 0C8000h-0CFFFFh 64/32 0C0000h-0C7FFFh 64/32 0B8000h-0BFFFFh 64/32 0B0000h-0B7FFFh 64/32 0A8000h-0AFFFFh 64/32 0A0000h-0A7FFFh 64/32 098000h-09FFFFh 64/32 090000h-097FFFh 64/32 088000h-08FFFFh 64/32 080000h-087FFFh 64/32 078000h-07FFFFh 64/32 070000h-077FFFh 64/32 068000h-06FFFFh 64/32 060000h-067FFFh 64/32 058000h-05FFFFh 64/32 050000h-057FFFh 64/32 048000h-04FFFFh 64/32 040000h-047FFFh 64/32 038000h-03FFFFh 64/32 030000h-037FFFh 64/32 028000h-02FFFFh 64/32 020000h-027FFFh 64/32 018000h-01FFFFh 64/32 010000h-017FFFh 64/32 008000h-00FFFFh 64/32 000000h-007FFFh 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY FLASH MEMORY OPERATING MODES COMMAND STATE MACHINE Commands are issued to the command state machine (CSM) using standard microprocessor write timings. The CSM acts as an interface between external microprocessors and the internal write state machine (WSM). The available commands are listed in Table 3, their definitions are given in Table 4 and their descriptions in Table 5. Program and erase algorithms are automated by the on-chip WSM. Table 7 shows the CSM transition states. Once a valid PROGRAM/ERASE command is entered, the WSM executes the appropriate algorithm, which generates the necessary timing signals to control the device internally. A command is valid only if the exact sequence of WRITEs is completed. After the WSM completes its task, the write state machine status (WSMS) bit (SR7) (see Table 8) is set to a logic HIGH level (VIH), allowing the CSM to respond to the full command set again. OPERATIONS Device operations are selected by entering a standard JEDEC 8-bit command code with conventional microprocessor timings into an on-chip CSM through I/Os DQ0-DQ7. The number of bus cycles required to activate a command is typically one or two. The first operation is always a WRITE. Control signals F_CE# and F_WE# must be at a logic LOW level (VIL), and F_OE# and F_RP# must be at logic HIGH (VIH). The second operation, when needed, can be a WRITE or a READ depending upon the command. During a READ operation, control signals F_CE# and F_OE# must be at a logic LOW level (VIL), and F_WE# and F_RP# must be at logic HIGH (VIH). Table 7 illustrates the bus operations for all the modes: write, read, reset, standby, and output disable. When the device is powered up, internal reset circuitry initializes the chip to a read array mode of operation. Changing the mode of operation requires that a command code be entered into the CSM. For each one of the two Flash memory partitions, an on-chip status register is available. These two registers allow the monitoring of the progress of various operations that can take place on a memory bank. One of the two status registers is interrogated by entering a READ STATUS REGISTER command onto the CSM (cycle 1), specifying an address within the memory partition boundary, and reading the register data on I/O pins DQ0-DQ7 (cycle 2). Status register bits SR0-SR7 correspond to DQ0-DQ7 (see Table 8). COMMAND DEFINITION Once a specific command code has been entered, the WSM executes an internal algorithm, generating the necessary timing signals to program, erase, and verify data. See Table 4 for the CSM command definitions and data for each of the bus cycles. STATUS REGISTER The status register allows the user to determine whether the state of a PROGRAM/ERASE operation is pending or complete. The status register is monitored by toggling F_OE# and F_CE# and reading the resulting status code on I/Os DQ0-DQ7. The high-order I/Os (DQ8-DQ15) are set to 00h internally, so only the loworder I/Os (DQ0-DQ7) need to be interpreted. Address lines select the status register pertinent to the selected memory partition. Table 3 Command State Machine Codes For Device Mode Selection COMMAND DQ0-DQ7 10h 20h 40h 50h 60h 60h 70h 90h 98h B0h C0h D0h D1h FFh CODE ON DEVICE MODE Accelerated Programming Algorithm (APA) Block erase setup Program setup Clear status register Protection configuration setup Enable/disable deep power-down Read status register Read protection configuration register Read query Program/erase suspend Protection register program/lock Program/erase resume - erase confirm Check block erase confirm Read array 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Register data is updated and latched on the falling edge of F_OE# or F_CE#, whichever occurs last. The latest falling edge of either of these two signals updates the latch within a given READ cycle. Latching the data prevents errors from occurring if the register input changes during a status register read. The status register provides the internal state of the WSM to the external microprocessor. During periods when the WSM is active, the status register can be polled to determine the WSM status. Table 8 defines the status register bits. After monitoring the status register during a PROGRAM/ERASE operation, the data appearing on DQ0-DQ7 remains as status register data until a new command is issued to the CSM. To return the device to other modes of operation, a new command must be issued to the CSM. COMMAND STATE MACHINE OPERATIONS The CSM decodes instructions for the commands listed in Table 3. The 8-bit command code is input to the device on DQ0-DQ7 (see Table 4 for command definitions). During a PROGRAM or ERASE cycle, the CSM informs the WSM that a PROGRAM or ERASE cycle has been requested. During a PROGRAM cycle, the WSM controls the program sequences and the CSM responds to a PROGRAM SUSPEND command only. During an ERASE cycle, the CSM responds to an ERASE SUSPEND command only. When the WSM has completed its task, the WSMS bit (SR7) is set to a logic HIGH level and the CSM responds to the full command set. The CSM stays in the current command state until the microprocessor issues another command. The WSM successfully initiates an ERASE or PROGRAM operation only when F_VPP is within its correct voltage range. Table 4 Command Definitions FIRST BUS CYCLE COMMAND OPERATION ADDRESS1 DATA READ ARRAY WRITE WA FFh READ PROTECTION CONFIGURATION REGISTER WRITE IA 90h READ STATUS REGISTER WRITE BA 70h CLEAR STATUS REGISTER WRITE BA 50h READ QUERY WRITE QA 98h BLOCK ERASE SETUP WRITE BA 20h PROGRAM SETUP WRITE WA 40h ACCELERATED PROGRAMMING ALGORITHM (APA) WRITE WA 10h PROGRAM/ERASE SUSPEND WRITE BA B0h PROGRAM/ERASE RESUME - ERASE CONFIRM WRITE BA D0h LOCK BLOCK WRITE BA 60h UNLOCK BLOCK WRITE BA 60h LOCK DOWN BLOCK WRITE BA 60h CHECK BLOCK ERASE WRITE BA 20h PROTECTION REGISTER PROGRAM WRITE PA C0h PROTECTION REGISTER LOCK WRITE LPA C0h ENABLE/DISABLE DEEP POWER-DOWN WRITE DPW 60h NOTE: 1. BA: Address within the block DPW:BBCFh = Disable deep power-down BBDFh = Enable deep power-down IA: Identification code address ID: Identification code data LPA: Lock protection register address PA: Protection register address PD: Data to be written at location PA QA: Query code address QD: Query code data SRD: Data read from the status register WA: Word address of memory location to be written, or read WD: Data to be written at the location WA X: "Don't Care" 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 SECOND BUS CYCLE OPERATION ADDRESS1 DATA1 READ READ READ WRITE WRITE WRITE IA X QA BA WA WA ID SRD QD D0h WD WD WRITE WRITE WRITE WRITE WRITE WRITE WRITE BA BA BA BA PA LPA DPW 01h D0h 2Fh D1h PD FFFDh 03h 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY FLASH Table 5 Command Descriptions CODE DEVICE MODE 10h 20h APA Erase Setup BUS CYCLE First First DESCRIPTION Prepares for an accelerated program operation. Prepares the CSM for the ERASE command. If the next command is not a CHECK BLOCK ERASE OR ERASE CONFIRM command, the command will be ignored, and the device will go to read status mode and wait for another command. A two-cycle command: The first cycle prepares for a PROGRAM operation, the second cycle latches addresses and data and initiates the WSM to execute the program algorithm. The Flash outputs status register data on the falling edge of F_OE# or F_CE#, whichever occurs first. The WSM can set the program status (SR4), and erase status (SR5) bits in the status register to "1," but it cannot clear them to "0." Issuing this command clears those bits to "0." Prepares the CSM for changes to the block locking status. If the next command is not BLOCK UNLOCK, BLOCK LOCK or BLOCK LOCK DOWN, the command will be ignored, and the device will go to read status mode. Puts the device into the set read configuration mode so that it will be possible to set the option bits related to burst read mode. Places the device into read status register mode. Reading the device outputs the contents of the status register for the addressed bank. The device automatically enters this mode for the addressed bank after a PROGRAM or ERASE operation has been initiated. Puts the device into the read protection configuration mode so that reading the device outputs the manufacturer/device codes or block lock status. Puts the device into the read query mode so that reading the device outputs common Flash interface information. Suspends the currently executing PROGRAM/ERASE/CHECK BLOCK ERASE operation. The status register indicates when the operation has been successfully suspended by setting either the program suspend (SR2) or erase suspend (SR6) and the WSMS bit (SR7) to a "1" (ready). The WSM continues to idle in the suspend state, regardless of the state of all input control pins except F_RP#, which immediately shuts down the WSM and the remainder of the chip if F_RP# is driven to VIL. Writes a specific code into the device protection register. Locks the device protection register; data can no longer be changed. 40h Program Setup First 50h Clear Status Register Protection Configuration Setup Set Read Configuration Register First 60h First First 70h Read Status Register First 90h Read Protection Configuration Read Query Program Suspend Erase Suspend Check Block Erase Suspend First 98h B0h First First First First C0h Program Device Protection Register Lock Device Protection Register First First (continued on the next page) 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY FLASH Table 5 Command Descriptions (continued) CODE DEVICE MODE D0h Erase Confirm BUS CYCLE Second DESCRIPTION If the previous command was an ERASE SETUP command, then the CSM closes the address and data latches, and it begins erasing the block indicated on the address pins. During programming/erase, the device responds only to the READ STATUS REGISTER, PROGRAM SUSPEND, or ERASE SUSPEND commands and outputs status register data on the falling edge of F_OE# or F_CE#, whichever occurs last. If a PROGRAM, ERASE or CHECK BLOCK ERASE operation was previously suspended, this command resumes the operation. During the array mode, array data is output on the data bus. If the previous command was PROTECTION CONFIGURATION SETUP, the CSM latches the address and locks the block indicated on the address bus. If the previous command was PROTECTION CONFIGURATION SETUP, the CSM latches the address and locks down the block indicated on the address bus. If the previous command was PROTECTION CONFIGURATION SETUP, the CSM latches the address and unlocks the block indicated on the address bus. If the block had been previously set to lock down, this operation has no effect. Unassigned command that should not be used. Second If the previous command was ERASE SETUP command, the CSM closes the address latches and checks that the block is completely erased. Program/Erase/ Check Block Erase Resume FFh 01h Read Array Lock Block First First Second 2Fh Lock Down Second D0h Unlock Block Second 00h D1h Invalid/Reserved Check Block Erase Confirm 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY CLEAR STATUS REGISTER The internal circuitry can set, but not clear, the block lock status bit (SR1), the F_VPP status bit (SR3), the program status bit (SR4), and the erase status bit (SR5) of the status register. The CLEAR STATUS REGISTER command (50h) allows the external microprocessor to clear these status bits and synchronize to the internal operations. When the status bits are cleared, the device returns to the read array mode. lines. Control signals F_CE# and F_OE# must be at a logic LOW level (VIL), and F_WE# and F_RP# must be at a logic HIGH level (VIH) to read data from the protection configuration register. Data is available on DQ0-DQ15. After data is read from protection configuration register, the READ ARRAY command, FFh, must be issued to the bank containing address 00h prior to issuing other commands. See Table 10 for further details. READ QUERY The read query mode outputs common flash interface (CFI) data when the device is read (see Table 12). Two bus cycles are required for this operation. It is possible to access the query by writing the read query command code 98h on DQ0-DQ7 to the bank containing address 0h. Control signals F_CE# and F_OE# must be at a logic LOW level (VIL), and F_WE# and F_RP# must be at a logic HIGH level (VIH) to read data from the query. The CFI data structure contains information such as block size, density, command set, and electrical specifications. To return to read array mode, write the read array command code FFh on DQ0-DQ7. READ STATUS REGISTER The status register is read by entering the command code 70h on DQ0-DQ7. Two bus cycles are required for this operation: one to enter the command code and a second to read the status register. In a READ cycle, the address is latched and register data is updated on the falling edge of F_OE# or F_CE#, whichever occurs last. Register data is updated and latched on the falling edge of F_OE# or F_CE#, whichever occurs last. READ OPERATIONS The following READ operations are available: READ ARRAY, READ PROTECTION CONFIGURATION REGISTER, READ QUERY and READ STATUS REGISTER. READ ARRAY The array is read by entering the command code FFh on DQ0-DQ7. Control signals F_CE# and F_OE# must be at a logic LOW level (VIL), and F_WE# and F_RP# must be at a logic HIGH level (VIH) to read data from the array. Data is available on DQ0-DQ15. Any valid address within any of the blocks selects that address and allows data to be read from that address. Upon initial power-up or device reset, the device defaults to the read array mode. READ CHIP PROTECTION IDENTIFICATION DATA The chip identification mode outputs three types of information: the manufacturer/device identifier, the block locking status, and the protection register. Two bus cycles are required for this operation: the chip identification data is read by entering the command code 90h on DQ0-DQ7 to the bank containing address 00h and the identification code address on the address 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY FLASH Present state of the other partition 1 Read array Read array 2 Read array OTP setup Lock Read query Read ID Read array Read status Read array Read array Read array Read array 5 6 Read array Read array 7 Read array OTP setup Lock Read query Read ID Read array Read status Read array Read array Read array Read array Read 11 Read array Read array 12 Read array OTP setup Lock Read query Read ID Read array Read status Read array Read array Read array Read array 15 16 Read array Read array 17 Read array OTP setup Lock Read query Read ID Read array Read status Read array Read array Read array Read array Protection register busy Protection register busy 1 0 Status Status Setup Busy P r o t e c t i o n r e g i s t e r 20 21 22 23 24 25 Erase setup Program Read setup array 1 Status Status 18 19 Busy Idle Erase suspend Prog. suspend Idle Idle Setup Busy Idle Erase suspend Prog. suspend Erase setup Program Read setup array 1 ID Device ID 13 14 Busy Idle Erase suspend Prog. suspend Setup 10 Erase setup Program Read setup array 1 CFI Query 8 9 Busy Idle Erase suspend Prog. suspend Setup Erase setup Program Read setup array 1 Array Array 3 4 Busy Idle Erase suspend Prog. suspend Setup Setup 26 27 Table 6 Command State Machine Transition Table Command input to the present partition (and next state of the present partition) 2Fh 01h Lock Lock down confirm confirm C0h 60h OTP Lock/Unlock setup /Lock down 98h Read query 90h Read device ID 50h 70h Clear Read status status register B0h Program /Erase suspend D0h BE confirm, P/E resume, ULB confirm 20h 10h/40h FFh Erase APA/ Read setup Program array setup Present state of the present partition Data when read SR7 State Mode Read array Lock Read query Read ID Read array Read status Read array 1 Status Done Read array OTP setup Lock Read query Read ID Read array Read status Read array Erase setup Program Read setup array 1 Status Done Read array Read array Read array (continued on next page) 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY FLASH Present state of the other partition 28 29 Read array OTP setup Read array 30 Read array Read query Read array Read status Read array Read array Read array Read array Lock 33 34 Read array OTP setup Read array 35 Read array Read query Read array Read status Read array Read array Read array Read array Program Busy Program Busy PS read Program busy 1 0 Status Status Setup Busy 38 39 40 41 Read array Read array Program Read array OTP setup Lock Read query Read ID Read array Read status Read array Read array Read array Read array 45 46 1 Status Read status Program suspend 47 48 Erase setup Program Read setup array 1 Status Done 42 43 44 Busy Idle Erase suspend Prog. suspend Setup Idle Erase suspend Erase setup Program Read setup array Lock/ Unlock 36 37 Busy Idle Erase suspend Prog. suspend Any state Idle Setup Erase setup Program Read setup array 31 32 Busy Idle Erase suspend Prog. suspend Setup Any state Setup Table 6 Command State Machine Transition Table (continued) Command input to the present partition (and next state of the present partition) 2Fh 01h Lock Lock down confirm confirm LB/ULB C0H 60h OTP Lock/Unlock setup /Lock down 98h Read query 90h 50h Read Clear device ID status register Lock 70h Read status B0h Program /Erase suspend L D0h BE confirm, P/E resume, ULB confirm LB/ULB 20h 10h/40h FFh Erase APA/ Read setup Program array setup Lock Present state of the present partition Data when read Status SR7 State Mode 1 Setup Lock Read ID 1 Status Error Lock Read ID 1 Status Program suspend read array Lock Program suspend read query Program suspend read ID Program suspend read array Program Program suspend suspend Program suspend read Program busy read read array status array (continued on next page) 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY FLASH Present state of the other partition 49 Program suspend read array 1 Array Read array 50 51 52 Program suspend read array Lock Program suspend read query Program suspend read ID Program suspend read array Program Program suspend suspend Program busy read read status array Program suspend read array 1 Table 6 Command State Machine Transition Table (continued) Command input to the present partition (and next state of the present partition) 2Fh 01h Lock Lock down confirm confirm C0h 60h OTP Lock/Unlock setup /Lock down 98h Read query 90h 50h Read Clear device ID status register 70h Read status B0h Program /Erase suspend D0h BE confirm, P/E resume, ULB confirm 20h 10h/40h FFh Erase APA/ Read setup Program array setup Present state of the present partition Data when read SR7 State Mode Program suspend read array Lock Program suspend read query Program suspend read ID Program suspend read array Program Program suspend suspend Program busy read read array status Setup Idle Erase suspend Setup Idle Erase suspend Setup Idle Erase suspend Idle Setup Busy Idle Erase suspend Prog. suspend Setup Busy Idle Erase suspend Prog. suspend Idle ID Read ID Program suspend 53 54 55 Program suspend read array Lock Program suspend read query Program suspend read ID Program suspend read array Program Program suspend suspend Program busy read read status array Erase error Program suspend read array 1 CFI Read Query 56 57 LB/ULB Erase error Erase busy Erase error 1 Status Setup 58 59 Read array OTP setup Read array 60 Erase setup Program Read setup array Read array Lock Read query Read ID Read array Read status Read array Read array 1 Status Error 61 62 63 Erase 64 Read array Read array Read array OTP setup Read array 65 Read array Lock Read query Read ID Read array Read status Read array Read array Erase Program Read setup array 1 Status Done 66 67 68 Read array Read array Block erase busy ES read status Erase busy 0 Status Busy 69 (continued on next page) 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY FLASH Present state of the other partition 70 71 ES read array 1 Table 6 Command State Machine Transition Table (continued) Command input to the present partition (and next state of the present partition) 2Fh 01h Lock Lock down confirm confirm C0h 60h OTP Lock/Unlock setup /Lock down 98h Read query 90h 50h Read Clear device ID status register 70h Read status B0h Program /Erase suspend ES read array Erase suspend read query Erase suspend read ID Erase suspend read array Erase suspend read status D0h BE confirm, P/E resume, ULB confirm Erase busy 20h 10h/40h FFh Erase APA/ Read setup Program array setup Erase suspend read array Present state of the present partition Data when read SR7 State Mode Setup Busy Idle Prog. suspend Setup Busy Idle Prog. suspend Setup Busy Erase suspend read array ES read array Erase busy ES read array Prog. setup Status Read status Erase suspend read array Lock 72 Erase suspend read array ES read array Erase suspend read query Erase suspend read ID Erase suspend read array Erase suspend read status Erase busy Erase suspend read array 73 74 75 ES read array 1 Array Read array 76 Erase suspend read array ES read array Erase busy ES read array Prog. setup Erase suspend read array Lock Erase suspend read array ES read array Erase suspend read query Erase suspend read ID Erase suspend read array Erase suspend read status Erase busy Erase suspend read array Erase suspend 77 78 79 ES read array 1 Erase suspend read array ES read array ES read array Prog. setup ID Read ID Erase suspend read array Lock Erase busy 80 Idle Prog. suspend Setup Busy Erase suspend read array ES read array Erase suspend read query Erase suspend read ID Erase suspend read array Erase suspend read status Erase busy Erase suspend read array 81 82 83 ES read array 1 CFI Read query Erase suspend read array ES read array ES read array Prog. setup Erase suspend read array Lock Erase busy 84 Idle Prog. suspend Erase suspend read array 85 Table 7 Bus Operations MODE Read (array, status registers, device identification register, or query) Standby Output Disable Reset Write F_RP# VIH F_CE# VIL F_OE# VIL F_WE# VIH ADDRESS DQ0-DQ15 X DOUT VIH VIL VIL VIH VIH VIH X VIL X VIH X VIH X VIH X VIL X X X X High-Z High-Z High-Z DIN 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY PROGRAMMING OPERATIONS There are two CSM commands for programming: PROGRAM SETUP and ACCELERATED PROGRAMMING ALGORITHM (see Table 3). PROGRAM SETUP COMMAND After the 40h command code is entered on DQ0- DQ7, the WSM takes over and correctly sequences the device to complete the PROGRAM operation. The WRITE operation may be monitored through the status register (see the Status Register section). During this time, the CSM will only respond to a PROGRAM SUSPEND command until the PROGRAM operation has been completed, after which time, all commands to the CSM become valid again. The PROGRAM operation can be suspended by issuing a PROGRAM SUSPEND command (B0h). Once the WSM reaches the suspend state, it allows the CSM to respond only to READ ARRAY, READ STATUS REGISTER, READ PROTECTION CONFIGURATION, READ QUERY, PROGRAM SETUP, or PROGRAM RESUME. During the PROGRAM SUSPEND operation, array data should be read from an address other than the one being programmed. To resume the PROGRAM operation, a PROGRAM RESUME command (D0h) must be issued to cause the CSM to clear the suspend state previously set (see Figure 4 for programming operation and Figure 5 for program suspend and program resume). Taking RP# to VIL during programming aborts the PROGRAM operation. ACCELERATED PROGRAMMING ALGORITHM The accelerated programming algorithm (APA) is intended for in-system and in-factory use. Its 32 single-word internal buffer enables fast data stream programming. The APA is activated when the WSM executes command code 10h. Upon activation, the word address and the data sequences must be provided to the WSM, without polling SR7. The same starting address must be provided for each data word. After all 32 sequences are issued, the status register reports a busy condition. Figure 6 shows the APA flowchart. If the data stream is shorter than 32 words, use FFFFh to fill in the missing data. Also, be sure the starting address is aligned with a 32-word boundary. The APA is fully concurrent. For example, it can be interrupted and resumed during programming. When loading the programming buffer, only a read access in the other bank is allowed. For in-factory programming, the APA, along with an optimized set of programming parameters, minimizes chip programming time when 11.4V F_VPP 12.6V. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 For in-system programming, when 0.9V F_VPP 2.2V, the APA and the 32 single-word buffer significantly improve both the system throughput and the average programming time when compared with standard programming practices. The accelerated programming functionality executes and verifies the APA without microprocessor intervention. This relieves the microprocessor from constantly monitoring the progress of the programming and erase activity, freeing up valuable memory bus bandwidth. This increases the system throughput. ERASE OPERATIONS An ERASE operation must be used to initialize all bits in an array block to "1s." After BLOCK ERASE confirm is issued, the CSM responds only to an ERASE SUSPEND command until the WSM completes its task. Block erasure inside the memory array sets all bits within the address block to logic 1s. Erase is accomplished only by blocks; data at single address locations within the array cannot be erased individually. The block to be erased is selected by using any valid address within that block. Block erasure is initiated by a command sequence to the CSM: BLOCK ERASE SETUP (20h) followed by BLOCK ERASE CONFIRM (D0h) (see Table 5). A two-command erase sequence protects against accidental erasure of memory contents. When the BLOCK ERASE CONFIRM command is complete, the WSM automatically executes a sequence of events to complete the block erasure. During this sequence, the block is programmed with logic 0s, data is verified, all bits in the block are erased, and finally verification is performed to ensure that all bits are correctly erased. Monitoring of the ERASE operation is possible through the status register (see the Status Register section). During the execution of an ERASE operation, the ERASE SUSPEND command (B0h) can be entered to direct the WSM to suspend the ERASE operation. Once the WSM has reached the suspend state, it allows the CSM to respond only to the READ ARRAY, READ STATUS REGISTER, READ QUERY, READ CHIP PROTECTION CONFIGURATION, PROGRAM SETUP, PROGRAM RESUME, ERASE RESUME and LOCK SETUP (see the Block Locking section). During the ERASE SUSPEND operation, array data must be read from a block other than the one being erased. To resume the ERASE operation, an ERASE RESUME command (D0h) must be issued to cause the CSM to clear the suspend state previously set (see Figure 8). It is also possible that an ERASE in any bank can be suspended and a WRITE to another block in the same bank can be initiated. After 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY the completion of a WRITE, an ERASE can be resumed by writing an ERASE RESUME command. After an ERASE command completion, it is possible to check if the block has been erased successfully, using the CHECK BLOCK ERASE command. Two bus cycles are required for this operation: one to set up the CHECK BLOCK ERASE and the second one to start the execution of the command. If after the operation the bit SR5 is set to 0 the operation has been completed succesfully, if it is set to 1, there has been an error during the BLOCK ERASE operation. Table 8 Status Register Bit Definition WSMS 7 ESS 6 ES 5 PS 4 VPPS 3 PSS 2 BLS 1 R 0 STATUS BIT # STATUS REGISTER BIT SR7 DESCRIPTION WRITE STATE MACHINE STATUS (WSMS) Check write state machine bit first to determine word 1 = Ready program or block erase completion, before checking 0 = Busy program or erase status bits. ERASE SUSPEND STATUS (ESS) 1 = BLOCK ERASE Suspended 0 = BLOCK ERASE in Progress/Completed ERASE/CHECK BLOCK ERASE STATUS (ES) 1 = Error in BLOCK ERASE/ CHECK BLOCK ERASE 0 = Successful BLOCK ERASE PROGRAM STATUS (PS) 1 = Error in PROGRAM 0 = Successful PROGRAM When ERASE SUSPEND is issued, WSM halts execution and sets both WSMS and ESS bits to "1." ESS bit remains set to "1" until an ERASE RESUME command is issued. When this bit is set to "1" and ERASE CONFIRM is issued, WSM has applied the maximum number of erase pulses to the block and is still unable to verify successful block erasure. When this bit is set to "1" and CHECK BLOCK ERASE CONFIRM is issued, WSM has checked the block for its erase state, and the block is not erased. When this bit is set to "1," WSM has attempted but failed to program a word. SR6 SR5 SR4 SR3 F_VPP STATUS (VPPS) The F_VPP status bit does not provide continuous indication 1 = F_VPP Low Detect, Operation Abort of the F_VPP level. The WSM interrogates the F_VPP level only 0 = F_VPP = OK after the program or erase command sequences have been entered and informs the system if F_VPP < 0.9V. The F_VPP level is also checked before the PROGRAM/ERASE operation is verified by the WSM. A factory option allows PROGRAM or ERASE at 0V, in which case SR3 is held at "0." PROGRAM SUSPEND STATUS (PSS) 1 = PROGRAM Suspended 0 = PROGRAM in Progress/Completed BLOCK LOCK STATUS (BLS) 1 = PROGRAM/ERASE Attempted on a Locked Block; Operation Aborted 0 = No Operation to Locked Blocks RESERVED FOR FUTURE ENHANCEMENT When PROGRAM SUSPEND is issued, WSM halts execution and sets both WSM and PSS bits to "1." PSS bit remains set to "1" until a PROGRAM RESUME command is issued. If a PROGRAM or ERASE operation is attempted to one of the locked blocks, this is set by the WSM. The operation specified is aborted, and the device is returned to read status mode. This bit is reserved for future use. SR2 SR1 SR0 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY FLASH Figure 4 Automated Word Programming Flowchart Start BUS OPERATION COMMAND COMMENTS WRITE WRITE PROGRAM SETUP WRITE DATA Data = Addr = Data = Addr = READ 40h Address of word to be programmed Word to be programmed Address of word to be programmed WRITE Issue PROGRAM SETUP Command and Word Address Issue Word Address and Word Data Status register data; toggle OE# or CE# to update status register. Check SR7 1 = Ready, 0 = Busy Standby Read Status Register Bits NO NO SR7 = 1? YES Full Status Register Check (optional)1 PROGRAM SUSPEND? PROGRAM SUSPEND Loop Repeat for subsequent words. Write FFh after the last word programming operation to reset the device to read array mode. YES Word Program Completed FULL STATUS REGISTER CHECK FLOW Read Status Register Bits BUS OPERATION COMMAND COMMENTS Standby Standby Check SR1 1 = Detect locked block Check SR32 1 = Detect F_VPP low Check SR43 1 = Word program error SR1 = 0? YES NO PROGRAM Attempted on a Locked Block Standby NO SR3 = 0? YES NO SR4 = 0? YES Word Program Passed VPP Range Error Word Program Failed NOTE: 1. Full status register check can be done after each word or after a sequence of words. 2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations. 3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation attempts. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY FLASH Figure 5 PROGRAM SUSPEND/ PROGRAM RESUME Flowchart Start BUS OPERATION COMMAND COMMENTS WRITE READ PROGRAM SUSPEND Data = B0h Status register data; toggle OE# or CE# to update status register. Check SR7 1 = Ready Check SR2 1 = Suspended READ MEMORY Data = FFh Read data from block other than that being programmed. PROGRAM RESUME Data = D0h Issue PROGRAM SUSPEND Command Standby Standby Read Status Register Bits WRITE READ WRITE NO SR7 = 1? YES NO SR2 = 1? YES Issue READ ARRAY Command PROGRAM Complete Finished Reading ? YES Issue PROGRAM RESUME Command NO PROGRAM Resumed 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY COMMENTS WRITE Start WRITE WRITE Data = 10h ACCELERATED Addr = Start address PROGRAM ALGORITHM SETUP WRITE DATA Data = Word to be programmed Addr = Start address Status register data Toggle OE# or CE# to update status register. Check SR7 1 = Ready, 0 = Busy NO SR3 = 0? READ YES Issue the ALTERNATE PROGRAM SETUP Command (10h) and Word Address Standby Issue 32 sequences of Word Address and Word Data NO SR7 = 0? YES PROGRAM Complete 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH Figure 6 Accelerated Program Algorithm Flowchart BUS OPERATION COMMAND ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY FLASH Figure 7 BLOCK ERASE Flowchart Start Issue ERASE SETUP Command and Block Address BUS OPERATION COMMAND COMMENTS WRITE WRITE ERASE SETUP ERASE Data = 20h Block Addr = Address within block to be erased Data = D0h Block Addr = Address within block to be erased Status register data; toggle OE# or CE# to update status register. Check SR7 1 = Ready, 0 = Busy WRITE READ Issue BLOCK ERASE CONFIRM Command and Block Address Standby ERASE SUSPEND Loop NO NO Read Status Register Bits Repeat for subsequent blocks. Write FFh after the last BLOCK ERASE operation to reset the device to read array mode. SR 7 = 1? YES Full Status Register Check (optional)1 ERASE SUSPEND? YES BLOCK ERASE Completed FULL STATUS REGISTER CHECK FLOW Read Status Register Bits BUS OPERATION COMMAND COMMENTS Standby Standby Standby ERASE Attempted on a Locked Block Check SR1 1 = Detect locked block Check SR32 1 = Detect F_VPP block Check SR4 and SR5 1 = BLOCK ERASE command error Check SR53 1 = BLOCK ERASE error NO SR1 = 0? YES NO SR3 = 0? YES NO SR5 = 0? YES BLOCK ERASE Passed Standby VPP Range Error BLOCK ERASE Failed NOTE: 1. Full status register check can be done after each block or after a sequence of blocks. 2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations. 3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full status is checked. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY FLASH Figure 8 ERASE SUSPEND/ERASE RESUME Flowchart Start BUS OPERATION COMMAND COMMENTS WRITE READ ERASE SUSPEND Data = B0h Status register data; toggle OE# or CE# to update status register. Check SR7 1 = Ready Check SR6 1 = Suspended READ MEMORY Data = FFh Read data from block other than that being erased. ERASE RESUME Data = D0h Issue ERASE SUSPEND Command Standby Standby Read Status Register Bits WRITE READ NO SR7 = 1? WRITE YES NO SR6 = 1? YES ERASE Complete PROGRAM READ or PROGRAM? READ Issue READ ARRAY Command PROGRAM Loop (Note 1) NO READ or PROGRAM Complete? YES Issue ERASE RESUME Command ERASE Continued2 NOTE: 1. See Word Programming Flowchart for complete programming procedure. 2. See BLOCK ERASE Flowchart for complete erasure procedure. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY FLASH Figure 9 CHECK BLOCK ERASE Flowchart Start BUS OPERATION COMMAND COMMENTS WRITE ERASE SETUP Data = 20h Block Addr = Address within block to be checked Data = D1 Block Addr = Address within block to be checked Status register data Toggle OE# or CE# to update status register Check SR7 and SR5 Issue ERASE SETUP Command and Block Address WRITE CHECK BLOCK ERASE CONFIRM READ Issue CHECK BLOCK ERASE CONFIRM Command and Block Address Standby NO SR7 = 1? YES NO SR5 = 0? YES BLOCK ERASE Complete Error 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY FLASH READ-WHILE-WRITE/ERASE CONCURRENCY It is possible for the device to read from one bank while erasing/writing to another bank. Once a bank enters the WRITE/ERASE operation, the other bank automatically enters read array mode. For example, during a READ CONCURRENCY operation, if a PROGRAM/ERASE command is issued in bank a, then bank a changes to the read status mode and bank b defaults to the read array mode. The device reads from bank b if the latched address resides in bank b (see Figure 10). Similarly, if a PROGRAM/ERASE command is issued in bank b, then bank b changes to read status mode and bank a defaults to read array mode. When returning to bank a, the device reads program/erase status if the latched address resides in bank a. A correct bank address must be specified to read status register after returning from concurrent read in the other bank. When reading the CFI or the chip protection register, concurrent operation is not allowed on the top boot device. Concurrent READ of the CFI or the chip protection register is only allowed when a PROGRAM or ERASE operation is performed on bank b on the bottom boot device. For a bottom boot device, reading of the CFI table or the chip protection register is only allowed if bank b is in read array mode. For a top boot device, reading of the CFI table or the chip protection register is only allowed if bank a is in read array mode. LOCKED STATE After a power-up sequence completion, or after a reset sequence, all blocks are locked (states [001] or [101]). This means full protection from alteration. Any PROGRAM or ERASE operations attempted on a locked block will return an error on bit SR1 of the status register. The status of a locked block can be changed to unlocked or lock down using the appropriate software commands. Writing the lock command sequence, 60h followed by 01h, can lock an unlocked block. UNLOCKED STATE Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks return to the locked state when the device is reset or powered down. An unlocked block can be locked or locked down using the appropriate software command sequence, 60h followed by D0h. (See Table 4.) Figure 10 READ-While-WRITE Concurrency Bank a 1 - Erasing/writing to bank a 2 - Erasing in bank a can be suspended, and a WRITE to another block in bank a can be initiated. 3 - After the WRITE in that block is complete, an ERASE can be resumed by writing an ERASE RESUME command. 1 - Reading bank a Bank b BLOCK LOCKING The Flash memory of the MT28C6428P20 and MT28C6428P18 devices provide a flexible locking scheme which allows each block to be individually locked or unlocked with no latency. The devices offer two-level protection for the blocks. The first level allows software-only control of block locking (for data which needs to be changed frequently), while the second level requires hardware interaction before locking can be changed (code which does not require frequent updates). Control signals F_WP#, DQ0, and DQ1 define the state of a block; for example, state [001] means F_WP# = 0, DQ0 = 0 and DQ1 = 1. Table 9 defines all of the possible locking states. NOTE: All blocks are software-locked upon completion of the power-up sequence. 1 - Reading from bank b 1 - Erasing/writing to bank b 2 - Erasing in bank b can be suspended, and a WRITE to another block in bank b can be initiated. 3 - After the WRITE in that block is complete, an ERASE can be resumed by writing an ERASE RESUME command. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY FLASH Table 9 Block Locking State Transition F_WP# 0 0 0 1 1 1 1 DQ1 0 0 1 0 0 1 1 DQ0 0 1 1 0 1 0 1 NAME Unlocked Locked (Default) Lock Down Unlocked Locked Lock Down Disabled Lock Down Disabled ERASE/PROGRAM ALLOWED Yes No No Yes No Yes No LOCK To [001] - - To [101] - To [111] - UNLOCK - To [000] - - To [100] - To [110] LOCK DOWN To [011] To [011] - To [111] To [111] To [111] - LOCKED DOWN STATE Blocks locked down (state [011]) are protected from PROGRAM and ERASE operations, but their protection status cannot be changed using software commands alone. A locked or unlocked block can be locked down by writing the lock down command sequence, 60h followed by 2Fh. Locked down blocks revert to the locked state when the device is reset or powered down. The LOCK DOWN function is dependent on the F_WP# input. When F_WP# = 0, blocks in lock down [011] are protected from program, erase, and lock status changes. When F_WP# = 1, the LOCK DOWN function is disabled ([111]) and locked down blocks can be individually unlocked by a software command to the [110] state, where they can be erased and programmed. These blocks can then be relocked [111] and unlocked [110], as desired, as long as F_WP# remains HIGH. When F_WP# goes LOW, blocks that were previously locked down return to the lock down state [011] regardless of any changes made while F_WP# was HIGH. Device reset or power-down resets all locks, including those in lock down, to the locked state (see Table 10). READING A BLOCK'S LOCK STATUS The lock status of every block can be read in the read device identification mode. To enter this mode, write 90h to the bank containing address 00h. Subsequent READs at block address +00002h will output the lock status of that block. The lowest two outputs, DQ0 and DQ1, represent the lock status. DQ0 indicates the block lock/unlock status and is set by the LOCK command and cleared by the UNLOCK command. It is also automatically set when entering lock down. DQ1 indicates lock down status and is set by the LOCK DOWN command. It can only be cleared by reset or powerdown, not by software. Table 9 shows the block locking state transition scheme. The READ ARRAY command, 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 FFh, must be issued to the bank containing address 00h prior to issuing other commands. LOCKING OPERATIONS DURING ERASE SUSPEND Changes to block lock status can be performed during an ERASE SUSPEND by using the standard locking command sequences to unlock, lock, or lock down. This is useful in the case when another block needs to be updated while an ERASE operation is in progress. To change block locking during an ERASE operation, first write the ERASE SUSPEND command (B0h), then check the status register until it indicates that the ERASE operation has been suspended. Next, write the desired lock command sequence to block lock, and the lock status will be changed. After completing any desired LOCK, READ, or PROGRAM operations, resume the ERASE operation with the ERASE RESUME command (D0h). If a block is locked or locked down during an ERASE SUSPEND on the same block, the locking status bits are changed immediately. When the ERASE is resumed, the ERASE operation completes. A locking operation cannot be performed during a PROGRAM SUSPEND. STATUS REGISTER ERROR CHECKING Using nested locking or program command sequences during ERASE SUSPEND can introduce ambiguity into status register results. Following protection configuration setup (60h), an invalid command produces a lock command error (SR4 and SR5 are set to "1") in the status register. If a lock command error occurs during an ERASE SUSPEND, SR4 and SR5 are set to "1" and remain at "1" after the ERASE SUSPEND command is issued. When the ERASE 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY is complete, any possible error during the ERASE cannot be detected via the status register because of the previous locking command error. A similar situation happens if an error occurs during a program operation error nested within an ERASE SUSPEND. 88h CHIP PROTECTION REGISTER A 128-bit chip protection register can be used to fullfill the security considerations in the system (preventing device substitution). The 128-bit security area is divided into two 64-bit segments. The first 64 bits are programmed at the manufacturing site with a unique 64-bit number. The other segment is left blank for customers to program as desired. (See Figure 12). READING THE CHIP PROTECTION REGISTER The chip protection register is read in the device identification mode. To enter this mode, load the 90h command the bank containing address 00h. Once in this mode, READ cycles from addresses shown in Table 10 retrieve the specified information. To return to the read array mode, write the READ ARRAY command (FFh). The READ ARRAY command, FFh, must be issued to the bank containing address 00h prior to issuing other commands. 85h 84h 4 Words User-Programmed 4 Words Factory-Programmed 81h 80h PR Lock 0 PAGE READ MODE The initial portion of the page mode cycle is the same as the asynchronous access cycle. Holding CE# LOW and toggling addresses A0-A2 allows random access of other words in the page. The page size can be customized at the factory to four or eight words as required; but if no specification is made, the normal size is four words. ASYNCHRONOUS READ CYCLE When accessing addresses in a random order or when switching between pages, the access time is given by tAA. When F_CE# and F_OE# are LOW, the data is placed on the data bus and the processor can read the data. Table 10 Chip Configuration Addressing1 ITEM Manufacturer Code (x16) Device Code Top boot configuration Bottom boot configuration ADDRESS 2 00000h 00001h 44B6h 44B7h XX002h Lock DQ0 = 0 DQ0 = 1 DQ1 = 1 PR Lock Factory Data User Data DATA 002Ch * * Block Lock Configuration is unlocked * Block is locked Block * Block is locked down * Protection Register Lock Chip Chip Protection Register 1 Chip Protection Register 2 80h 81h-84h 85h-88h NOTE: 1. Other locations within the configuration address space are reserved by Micron for future use. 2. "XX" specifies the block address of lock configuration. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH Figure 12 Protection Register Memory Map ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY STANDBY MODE ICC supply current is reduced by applying a logic HIGH level on F_CE# and F_RP# to enter the standby mode. In the standby mode, the outputs are placed in High-Z. Applying a CMOS logic HIGH level on F_CE# and F_RP# reduces the current to ICC3 (MAX). If the device is deselected during an ERASE operation or during programming, the device continues to draw current until the operation is complete. A factory option provides in-system programming and erase with F_VPP in the 0.0V-2.2V range. F_VPP at 12V 5% (F_VPP2) is supported for a maximum of 100 cycles and 10 cumulative hours. The device can withstand 100,000 WRITE/ERASE operations when F_VPP = F_VCC. During WRITE and ERASE operations, the WSM monitors the F_VPP voltage level. WRITE/ERASE operations are allowed only when F_VPP is within the ranges specified in Table 11. When F_VCC is below VLKO or F_VPP is below VPPLK, any WRITE/ERASE operation is prevented. AUTOMATIC POWER SAVE (APS) MODE Substantial power savings are realized during periods when the Flash array is not being read and the device is in the active mode. During this time the device switches to the automatic power save (APS) mode. When the device switches to this mode, ICC is reduced to a level comparable to ICC3. Further power savings can be realized by applying a logic HIGH level on CE# to place the device in standby mode. The low level of power is maintained until another operation is initiated. In this mode, the I/Os retain the data from the last memory address read until a new address is read. This mode is entered automatically if no addresses or control signals toggle. DEVICE RESET To correctly reset the device, the RST# signal must be asserted (RST# = VIL) for a minimum of tRP. After reset, the device can be accessed for a READ operation with a delayed access time of tRWH from the rising edge of RST#. The circuitry used for generating the RST# signal needs to be common with the rest of the system reset to ensure that correct system initialization occurs. Please refer to the timing diagram for further details. DEEP POWER-DOWN MODE By issuing an ENABLE DEEP POWER-DOWN command (see Table 3) it is possible to enable the DEEP POWER-DOWN function. In this configuration, applying a logic LOW to RST# reduces the current to ICC10, and resets all the internal registers with the exception of the individual block protection status. To exit this mode, a wait time of 100s (tRWHDP) must elapse after a logic HIGH is applied to RST#. During the wait time, the device performs a full power-up sequence, and the power consumption may exceed the standby current limits. POWER-UP SEQUENCE The following power-up sequence is recommended to properly initialize internal chip operations: * At power-up, RST# should be kept at VIL for 2s after F_VCC reaches F_VCC (MIN). * VCCQ should not come up before F_VCC. * F_VPP should be kept at VIL to maximize data integrity. When the power-up sequence is completed, RST# should be brought to VIH. To ensure proper power-up, the rise time of RST# (10%-90%) should be < 10s. F_VPP/F_VCC PROGRAM AND ERASE VOLTAGES The Flash memory devices provide in-system programming and erase with F_VPP in the 0.9V-2.2V range. In addition to the flexible block locking, the F_VPP programming voltage can be held LOW for absolute hardware write protection of all blocks in the Flash device. When F_VPP is below VPPLK, any PROGRAM or ERASE operation results in an error, prompting the corresponding status register bit (SR3) to be set. DEVICE In-System In-Factory Table 11 F_VPP Ranges (V) MIN 0.9 11.4 MAX 2.2 12.6 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY FLASH ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS* Voltage to Any Ball Except F_VCC and F_VPP with Respect to VSS ............................ -0.5V to +2.45V F_VPP Voltage (for BLOCK ERASE and PROGRAM with Respect to VSS) ....................... -0.5V to +13.5V** F_VCC and VCCQ Supply Voltage with Respect to VSS ............................ -0.3V to +2.45V Output Short Circuit Current ............................... 100mA Operating Temperature Range .............. -40oC to +85oC Storage Temperature Range ................. -55oC to +125oC Soldering Cycle ........................................... 260oC for 10s *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Maximum DC voltage on F_VPP may overshoot to +13.5V for periods <20ns. RECOMMENDED OPERATING CONDITIONS (-40C TA +85C) PARAMETER VCC supply voltage (MT28C6428P18) VCC supply voltage (MT28C6428P20) I/O supply voltage (MT28C6428P18) I/O supply voltage (MT28C6428P20) F_VPP voltage (when used as logic control) F_VPP in-factory programming voltage Data retention supply voltage Block erase cycling (F_VPP1) F_VPP = F_VPP1 F_VPP = F_VPP2 SYMBOL F_VCC, S_VCC F_VCC, S_VCC VCCQ VCCQ F_VPP1 F_VPP2 S_VDR F_VPP1 F_VPP2 MIN 1.70 1.80 1.70 1.80 0.9 11.4 1.0 - - MAX 1.90 2.20 1.90 2.20 2.2 12.6 - 100,000 100 UNITS V V V V V V V Cycles Cycles 1 NOTES NOTE: 1. F_VPP = F_VPP2 is a maximum of 10 cumulative hours. Figure 13 AC Input/Output Reference Waveform VCC Input VSS VCC/2 Test Points VCCQ/2 Output AC test inputs are driven at VCC for a logic 1 and VSS for a logic 0. Input timing begins at VCC/2, and output timing ends at VCCQ/2. Input rise and fall times (10% to 90%) < 5ns. Figure 14 Output Load Circuit VCC 14.5K I/O 14.5K VSS 30pF 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY COMBINED DC CHARACTERISTICS1 F_VCC/VCCQ = 1.70V-1.90V or 1.80V-2.20V DESCRIPTION Input Low Voltage Input High Voltage Output Low Voltage IOL = 100A (Flash) Output Low Voltage IOL = 100A (SRAM) Output High Voltage IOH = -100A (Flash) Output High Voltage IOH = -100A (SRAM) F_VPP Lockout Voltage F_VPP During PROGRAM/ERASE Operations F_VCC Program/Erase Lock Voltage Input Leakage Current Output Leakage Current F_VCC Read Current Asynchronous Random Read, 100ns cycle Asynchronous Page Read, 100ns/35ns cycle F_VCC plus S_VCC Standby Current F_VCC Program Current F_VCC Erase Current F_VCC Erase Suspend Current F_VCC Program Suspend Current Read-While-Write Current NOTE: 1. 2. 3. 4. 5. 6. CONDITIONS SYMBOL VIL VIH VOL VOL VOH VOH VPPLK F_VPP1 F_VPP2 VLKO IL IOZ ICC1 MIN 0.0 VCCQ - 0.4 - - VCCQ - 0.1 VCCQ - 0.3 - 0.9 11.4 1.0 - - - TYP - - - - - - - - - - - - - - 25 - 18 6 6 - MAX 0.4 VCCQ 0.10 0.3 - - 0.4 2.2 12.6 - 1.0 1.0 15 5 70 55 45 70 70 80 UNITS NOTES V V V V V V V V V V A A 4, 5 mA mA A mA mA A A mA 6 6 4, 5 3 2 2 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 ICC8 - - - - - - - All currents are in RMS unless otherwise noted. VIL may decrease to -0.4V and VIH may increase to VCCQ + 0.3V for durations not to exceed 20ns. 12V F_VPP is supported for a maximum of 100 cycles and may be connected for up to 10 cumulative hours. APS mode reduces ICC to approximately ICC3 levels. Test conditions: Vcc = VCC (MAX), CE# = VIL, OE# = VIH. All other inputs = VIH or VIL. ICC6 and ICC7 values are valid when the device is deselected. Any read operation performed while in suspend mode will add a current draw of ICC1 or ICC2. (continued on next page) 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY COMBINED DC CHARACTERISTICS1 (continued) F_VCC/VCCQ = 1.70V-1.90V or 1.80V-2.20V DESCRIPTION S_VCC Read/Write Operating Supply Current - Random Access Mode S_VCC Read/Write Operating Supply Current - Page Access Mode Deep Power-Down Current F_VPP Current (Read, Standby Erase Suspend, Program Suspend) NOTE: 1. 2. 3. 4. 5. 6. CONDITIONS VIN = VIH or VIL chip enabled, IOL = 0 VIN = VIH or VIL chip enabled, IOL = 0 F_VPP F_VCC F_VPP F_VCC SYMBOL ICC9 MIN - TYP 12 MAX 15 UNITS NOTES mA ICC10 - 2 3 mA ICC11 IPP1 - 0.5 50 35 - - 45 1 200 A A A All currents are in RMS unless otherwise noted. VIL may decrease to -0.4V and VIH may increase to VCCQ + 0.3V for durations not to exceed 20ns. 12V F_VPP is supported for a maximum of 100 cycles and may be connected for up to 10 cumulative hours. APS mode reduces ICC to approximately ICC3 levels. Test conditions: Vcc = VCC (MAX), CE# = VIL, OE# = VIH. All other inputs = VIH or VIL. ICC6 and ICC7 values are valid when the device is deselected. Any read operation performed while in suspend mode will add a current draw of ICC1 or ICC2. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY CAPACITANCE (TA = +25C; f = 1 MHz) PARAMETER/CONDITION Input Capacitance Output Capacitance SYMBOL C COUT TYP 7 13 MAX 12 15 UNITS pF pF FLASH READ CYCLE TIMING REQUIREMENTS -80 F_VCC = 1.80V-2.20V MIN MAX 80 80 30 25 200 20 0 80 100 -85 F_VCC = 1.70V-1.90V MIN MAX 85 85 35 30 250 25 0 85 100 PARAMETER Address to output delay F_CE# LOW to output delay Page address access F_OE# LOW to output delay F_RP# HIGH to output delay CE# or OE# HIGH to output High-Z Output hold from address, CE# or OE# change READ cycle time RST# deep power-down SYMBOL tAA tACE t APA tAOE tRWH tOD tOH tRC tRWHOP UNITS ns ns ns ns ns ns ns ns s 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY FLASH WRITE CYCLE TIMING REQUIREMENTS -80 F_VCC = 1.80V-2.20V MIN MAX 150 0 50 50 50 0 0 0 30 0 200 50 0 0 0 tAA + 50 -85 F_VCC = 1.70V-1.90V MIN MAX 150 0 70 70 70 0 0 0 30 0 200 50 0 0 0 tAA + 50 PARAMETER Reset HIGH recovery to F_WE# going LOW F_CE# setup to F_WE# going LOW Write pulse width Data setup to F_WE# going HIGH Address setup to F_WE# going HIGH F_CE# hold from F_WE# HIGH Data hold from F_WE# HIGH Address hold from F_WE# HIGH Write pulse width HIGH F_WP# setup to F_WE# going HIGH F_VPP setup to F_WE# going HIGH Write recovery before READ Write recovery before READ in opposite bank F_WP# hold from valid SRD F_VPP hold from valid SRD F_WE# HIGH to data valid SYMBOL tRS tCS tWP tDS tAS tCH tDH tAH tWPH tRHS tVPS tWOS tWOA tRHH tVPPH tWB UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns FLASH ERASE AND PROGRAM CYCLE TIMING REQUIREMENTS -80/-85 PARAMETER 4KW parameter block program time 32KW parameter block program time Word program time 4KW parameter block erase time 32KW parameter block erase time Program suspend latency Erase suspend latency Chip programming time TYP 40 320 8 0.3 0.5 5 5 MAX 800 6,400 10,000 6 6 10 20 20 UNITS ms ms s s s s s S 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY TWO-CYCLE PROGRAMMING/ERASE OPERATION A0-A21 VIH VALID ADDRESS VIL VIH F_CE# VIL tCS tCH tWOS VALID ADDRESS tAS tAH VALID ADDRESS VIH F_OE# VIL VIH F_WE# VIL VOH DQ0-DQ15 VOL High-Z tRS tDH tRHS tWP tWB tWPH CMD CMD/ DATA tDS STATUS VIH F_RP# VI L VIH F_WP# VIL tRHH tVPS tVPPH VIPPH VIPPLK F_VPP V IL UNDEFINED WRITE TIMING PARAMETERS -80 F_VCC = 1.80V-2.20V SYMBOL tRS tCS tWP tDS tAS tCH tDH -85 F_VCC = 1.70V-1.90V MIN 150 0 70 70 70 0 0 MAX UNITS ns ns ns ns ns ns ns SYMBOL tAH tRHS tVPS tWOS tRHH tVPPH tWB -80 F_VCC = 1.80V-2.20V MIN 0 0 200 50 0 0 tAA + 50 -85 F_VCC = 1.70V-1.90V MIN 0 0 200 50 0 0 tAA + 50 MIN 150 0 50 50 50 0 0 MAX MAX MAX UNITS ns ns ns ns ns ns ns NOTE: 1. The WRITE cycles for the WORD PROGRAMMING command are followed by a READ ARRAY DATA cycle. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 36 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY SINGLE ASYNCHRONOUS READ OPERATION A0-A21 VIH VALID ADDRESS VIL tRC tAA tOD VIH F_CE# VIL tACE VIH F_OE# VIL tOH VIH F_WE# VIL VOH DQ0-DQ15 VOL tAOE High-Z tRWH VALID OUTPUT F_RP# VIH VIL UNDEFINED READ TIMING PARAMETERS -80 F_VCC = 1.80V-2.20V SYMBOL tAA tACE tAOE tRWH -85 F_VCC = 1.70V-1.90V MIN MAX 85 85 30 250 UNITS ns ns ns ns SYMBOL tOD tOH tRC -80 F_VCC = 1.80V-2.20V MIN 0 80 MAX 20 -85 F_VCC = 1.70V-1.90V MIN 0 85 MAX 25 UNITS ns ns ns MIN MAX 80 80 25 200 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 37 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY ASYNCHRONOUS PAGE MODE READ OPERATION A3-A21 VIH VALID ADDRESS VIL VIH VALID ADDRESS VIL tAA tOD A0-A2 VALID ADDRESS VALID ADDRESS VALID ADDRESS VIH F_CE# VIL tACE VIH F_OE# VIL VIH F_WE# VIL tAOE tAPA tOH VOH DQ0-DQ15 VOL High-Z tRMH VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VIH F_RP# VIL UNDEFINED READ TIMING PARAMETERS -80 F_VCC = 1.80V-2.20V SYMBOL tAA tACE t -85 F_VCC = 1.70V-1.90V MIN MAX 85 85 35 30 UNITS ns ns ns ns SYMBOL tRWH tOD tOH -80 F_VCC = 1.80V-2.20V MIN MAX 200 20 0 -85 F_VCC = 1.70V-1.90V MIN MAX 250 25 0 UNITS ns ns ns MIN MAX 80 80 30 25 APA tAOE 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 38 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY RESET OPERATION VIH VIL F_RST# VIH VIL tRP F_CE# F_OE# VIH VIL DQ0-DQ15 VOH VOL tRWH READ TIMING PARAMETERS -80 F_VCC = 1.80V-2.20V MIN MAX 200 100 -85 F_VCC = 1.70V-1.90V MIN MAX 250 100 SYMBOL tRWH tRP UNITS ns ns 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 39 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. FLASH ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY FLASH Table 12 CFI OFFSET 00 01 02-0F 10, 11 12 13, 14 15, 16 17, 18 19, 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A, 2B 2C 2D, 2E 2F, 30 31, 32 33, 34 35, 36 DATA 2Ch B6h B7h reserved 0051,0052 0059 0003, 0000 0039, 0000 0000, 0000 0000, 0000 0017 0022 00B4 00C6 0003 0000 0009 0000 000C 0000 0003 0000 0017 0001 0000 0000, 0000 0003 5F00, 0001 0007, 0000 0000, 0001 0020, 0000 000E, 0000 0000, 0001 0007, 0000 5F00, 0001 Manufacturer code Top boot block device code Bottom boot block device code Reserved "QR" "Y" Primary OEM command set Address for primary extended table Alternate OEM command set Address for OEM extended table F_VCC MIN for Erase/Write; Bit7-Bit4 Volts in BCD; Bit3-Bit0 100mV in BCD F_VCC MAX for Erase/Write; Bit7-Bit4 Volts in BCD; Bit3-Bit0 100mV in BCD F_VPP MIN for Erase/Write; Bit7-Bit4 Volts in Hex; Bit3-Bit0 100mV in BCD F_VPP MAX for Erase/Write; Bit7-Bit4 Volts in Hex; Bit3-Bit0 100mV in BCD, 0000 = F_VPP ball Typical timeout for single byte/word program, 2n s, 0000 = not supported Typical timeout for maximum size multiple byte/word program, 2n s, 0000 = not supported Typical timeout for individual block erase, 2n ms, 0000 = not supported Typical timeout for full chip erase, 2n ms, 0000 = not supported Maximum timeout for single byte/word program, 2n s, 0000 = not supported Maximum timeout for maximum size multiple byte/word program, 2n s, 0000 = not supported Maximum timeout for individual block erase, 2n ms, 0000 = not supported Maximum timeout for full chip erase, 2n ms, 0000 = not supported Device size, 2n bytes Bus interface x8 = 0, x16 = 1, x8/x16 = 2 Flash device interface description 0000 = async Maximum number of bytes in multibyte program or page, 2n Number of erase block regions within device (4K words and 32K words) Top boot block device erase block region information 1, 8 blocks ... Bottom boot block device erase block region information 1, 8 blocks ... Erase block region information 1, 8 blocks ... ...of 8KB 15 blocks of .... ......64KB Top boot block device ......96KB blocks of Bottom boot block device ......96KB blocks of (continued on the next page) 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 DESCRIPTION 40 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY FLASH Table 12 CFI (continued) OFFSET 37, 38 39, 3A 3B 3C 3D 3E 3F 40 41 DATA 0020, 0000 0000, 0001 0050, 0052 0049 0030 0031 00E6 0002 0000 0000 Top boot block device......64KB Bottom boot block device......64KB "PR" "I" Major version number, ASCII Minor version number, ASCII Optional Feature and Command Support Bit 0 Chip erase supported no = 0 Bit 1 Suspend erase supported = yes = 1 Bit 2 Suspend program supported = yes = 1 Bit 3 Chip lock/unlock supported = no = 0 Bit 4 Queued erase supported = no = 0 Bit 5 Instant individual block locking supported = yes = 1 Bit 6 Protection bits supported = yes = 1 Bit 7 Page mode read supported = yes = 1 Bit 8 Synchronous read supported = yes = 1 Bit 9 Simultaneous operation supported = yes = 1 Program supported after erase suspend = yes Bit 0 block lock status active = yes; Bit 1 block lock down active = yes F_VCC supply optimum; Bit7-Bit4 Volts in BCD; Bit3-Bit0 100mV in BCD F_VPP supply optimum; Bit7-Bit4 Volts in Hex; Bit3-Bit0 100mV in BCD Number of protection register fields in JEDEC ID space Lock bytes LOW address, lock bytes HIGH address 2n factory programmed bytes, 2n user programmable bytes Background Operation 0000 = Not used 0001 = 4% block split 0002 = 12% block split 0003 = 25% block split 0004 = 50% block split Burst 0000 00x1 00x2 00x3 001x 002x 004x Page 0000 0001 0002 0003 0004 Mode Type = No burst mode = 4 words MAX = 8 words MAX = 16 words MAX = Linear burst, and/or = Interleaved burst, and/or = Continuous burst Mode Type = No page mode = 4-word page = 8-word page = 16-word page = 32-word page DESCRIPTION 42 43, 44 45 46 47 48, 49 4A, 4B 4C 0001 0003,0000 0018 00C0 0001 0080, 0000 0003, 0003 0003 4D 0000 4E 0002 4F 0008 SRAM density, 8Mb (512K x 16) 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 41 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY SRAM OPERATING MODES SRAM READ ARRAY The operational state of the SRAM is determined by S_CE1#, S_CE2, S_WE#, S_OE#, S_UB#, and S_LB#, as indicated in the Truth Table. To perform an SRAM READ operation, S_CE1#, and S_OE#, must be at VIL, and S_CE2 and S_WE# must be at VIH. When in this state, S_UB# and S_LB# control whether the lower byte is read (S_UB# VIH, S_LB# VIL), the upper byte is read (S_UB# VIL, S_LB# VIH), both upper and lower bytes are read (S_UB# VIL, S_LB# VIL), or neither are read (S_UB# VIH, S_LB# VIH) and the device is in a standby state. While performing an SRAM READ operation, current consumption may be reduced by reading within a 16-word page. This is done by holding S_CE1# and S_OE# at VIL, S_WE# and S_CE2 at VIH, and toggling addresses A0-A3. S_UB# and S_LB# control the data width as described above. SRAM WRITE ARRAY In order to perform an SRAM WRITE operation, S_CE1# and S_WE# must be at VIL, and S_CE2 and S_OE# must be at VIH. When in this state, S_UB# and S_LB# control whether the lower byte is written (S_UB# VIH, S_LB# VIL), the upper byte is written (S_UB# VIL, S_LB# VIH), both upper and lower bytes are written (S_UB# VIL, S_LB# VIL), or neither are written (S_UB# VIH, S_LB# VIH) and the device is in a standby state. SRAM FUNCTIONAL BLOCK DIAGRAM WORD ADDRESS DECODE LOGIC A0-A3 A4-A18 PAGE ADDRESS DECODE LOGIC 16K-PAGE x16 WORD x16 BIT RAM ARRAY WORD MUX INPUT/ OUTPUT MUX AND BUFFERS DQ0-DQ7 DQ8-DQ15 S_CE1# S_CE2 S_WE# S_OE# S_UB# S_LB# CONTROL LOGIC 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 42 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. SRAM ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY TIMING TEST CONDITIONS Input pulse levels ........... 0.1V S_VCC to 0.9V S_VCC Input rise and fall times .................................... 5ns Input timing reference levels ......................... 0.5V Output timing reference levels ..................... 0.5V Operating Temperature ............... -40oC to +85oC NOTE: For input/output contacts, refer to the Capacitance Table. SRAM READ CYCLE TIMING -80 S_VCC = 1.80V-2.20V MIN MAX 80 80 25 80 20 80 0 0 0 0 15 0 15 0 15 5 -85 S_VCC = 1.70V-1.90V MIN MAX 85 85 25 85 20 85 0 0 0 0 15 0 15 0 15 5 DESCRIPTION READ cycle time Address access time Address access time (word mode) Chip enable to valid output Output enable to valid output Byte select to valid output Chip enable to Low-Z output Output enable to Low-Z output Byte select to Low-Z output Chip enable to High-Z output Output disable to High-Z output Byte select disable to High-Z output Output hold from address change SYMBOL t RC t AA t AAW t CO t OE tLB, tUB t LZ t OLZ tLBZ, tUBZ t HZ t OHZ tLBHZ, tUBHZ t OH UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns SRAM WRITE CYCLE TIMING -80 S_VCC = 1.80V-2.20V MIN MAX 80 80 80 80 0 50 0 0 15 30 0 0 -85 S_VCC = 1.70V-1.90V MIN MAX 85 85 85 85 0 50 0 0 15 30 0 0 DESCRIPTION WRITE cycle time Chip enable to end of write Address valid to end of write Byte select to end of write Address setup time Write pulse width Write recovery time Write to High-Z output Data to write time overlap Data hold from write time End write to Low-Z output 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 SYMBOL t WC t CW t AW tLBW, tUBW t AS t WP t WR t WHZ t DW t DH t OW UNITS ns ns ns ns ns ns ns ns ns ns ns 43 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. SRAM ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY READ CYCLE 1 (S_CE1# = S_OE# = VIL; S_CE2, S_WE# = VIH) tRC ADDRESS tOH DATA-OUT PREVIOUS DATA VALID DATA VALID READ CYCLE 2 (S_WE# = VIH) tRC ADDRESS tAA tHZ (1, 2) S_CE1# tCO S_CE2 tLZ(2) tOE tOHZ (1) S_OE# tOLZ tLB, tUB S_LB#, S_UB# tLBLZ, tUBLZ tLBHZ, tUBHZ DATA VALID DATA-OUT High-Z DON'T CARE READ TIMING PARAMETERS -80 S_VCC = 1.80V-2.20V SYMBOL tRC tAA tCO tOE tLB, tUB tLZ -85 S_VCC = 1.70V-1.90V MIN MAX 85 85 85 20 85 0 UNITS ns ns ns ns ns ns SYMBOL tOLZ tHZ tOHZ tLBHZ, tUBHZ tOH -80 S_VCC = 1.80V-2.20V MIN 0 0 0 0 5 MAX 15 15 15 -85 S_VCC = 1.70V-1.90V MIN 0 0 0 0 5 MAX 15 15 15 UNITS ns ns ns ns ns MIN MAX 80 80 80 20 80 0 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 44 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. SRAM tAA ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY WRITE CYCLE (S_WE# CONTROL) tWC ADDRESS tAW tWR S_CE1# tCW S_CE2 tLBW, tUBW S_LB#, S_UB# tAS tWP S_WE# tDW tDH DATA-IN High-Z tWHZ DATA VALID tOW DATA-OUT High-Z DON'T CARE WRITE TIMING PARAMETERS -80 S_VCC = 1.80V-2.20V MIN MAX 80 80 80 80 0 0 -85 S_VCC = 1.70V-1.90V MIN MAX 85 85 85 85 -80 S_VCC = 1.80V-2.20V MIN MAX 50 0 0 30 0 0 15 -85 S_VCC = 1.70V-1.90V MIN MAX 50 0 0 30 0 0 15 SYMBOL tWC tCW tAW tLBW, tUBW tAS UNITS ns ns ns ns ns SYMBOL tWP tWR tWHZ tDW tDH tOW UNITS ns ns ns ns ns ns 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 45 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. SRAM ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY WRITE CYCLE 2 (S_CE1# CONTROL) tWC ADDRESS tCW S_CE1# tAS tLBW, tUBW S_LB#, S_UB# tWP S_WE# tDW tDH DATA-IN tLZ tWHZ DATA VALID DATA-OUT High-Z DON'T CARE WRITE TIMING PARAMETERS -80 S_VCC = 1.80V-2.20V MIN MAX 80 80 80 80 0 0 -85 S_VCC = 1.70V-1.90V MIN MAX 85 85 85 85 -80 S_VCC = 1.80V-2.20V MIN MAX 50 0 0 30 0 0 15 -85 S_VCC = 1.70V-1.90V MIN MAX 50 0 0 30 0 0 15 SYMBOL tWC tCW tAW tLBW, tUBW tAS UNITS ns ns ns ns ns SYMBOL tWP tWR tWHZ tDW tDH tOW UNITS ns ns ns ns ns ns 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 46 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. SRAM tAW tWR ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY 67-BALL FBGA 1.05 0.075 SEATING PLANE C 0.12 C 67X 0.35 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PREREFLOW DIAMETER IS O 0.33 8.80 0.80 (TYP) BALL A1 ID 1.40 MAX BALL A1 ID BALL A12 4.50 0.05 BALL A1 5.60 2.80 0.05 0.80 (TYP) C L 9.00 0.10 C L 4.40 0.05 5.75 0.05 MOLD COMPOUND: EPOXY NOVOLAC SUBSTRATE: PLASTIC LAMINATE SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or 62% Sn, 36% Pb, 2%Ag SOLDER BALL PAD: O .27mm 11.50 0.10 NOTE: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.27mm per side. DATA SHEET DESIGNATION Advance: This data sheet contains initial descriptions of products still under development. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 47 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY REVISION HISTORY Rev. 3, ADVANCE .............................................................................................................................................................. 7/02 * Corrected bottom boot block device address ranges * Updated command descriptions * Updated SR5 status register bit description * Updated flowcharts * Updated DC Characteristics * Corrected Status Register section * Updated the Read-While-Write/Erase Concurrency section * Changed tRHS from 200ns (MIN) to 0ns (MIN) * Changed COUT from 9 (TYP) and 12 (MAX) to 13 (TYP) and 15 (MAX) Rev. 2, ADVANCE .............................................................................................................................................................. 4/02 * Updated the Combined DC Characteristics table * Updated tAH and tRWH * Updated the chip protection mode register information * Updated the block locking information Initial published release, ADVANCE, Rev. 1 ............................................................................................................... 1/02 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 - Rev. 3, Pub. 7/02 48 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. |
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